Are you looking for an exciting opportunity to join a dynamic and growing team in a fast paced and challenging area? This is a unique opportunity for you to work with Global Technology Applied Research (GTAR) center at JPMorganChase. The goal of GTAR is to design and conduct research across multiple frontier technologies, in order to enable novel discoveries and inventions, and to inform and develop next-generation solutions for the firm’s clients and businesses.

As an experienced engineer within GTAR, you will leverage your expertise in accelerator chips and advanced compute architectures for AI and emerging applications. This role requires a deep understanding of chip architectures and their performance at scale. You will evaluate how different accelerator chips—such as custom ASICs, wafer-scale architectures, and dataflow architectures perform across a range of workloads, identify their strengths and limitations, and help guide our research toward the most effective hardware solutions. The position also involves close collaboration with companies developing alternative chips to evaluate trade-offs, define requirements, and jointly develop optimized execution models for applications and workloads on new hardware.

Job Responsibilities

• Investigate and document the capabilities and limitations of modern accelerator architectures and advanced semiconductor systems, including ASICs, wafer-scale and dataflow architectures.
• Perform detailed analyses of compute, memory, interconnect, and execution model tradeoffs for a variety of workloads.
• Benchmark and assess accelerator platforms and emerging chip designs for AI, quantum simulation, and other advanced applications.
• Help advise leadership on opportunities where advanced chip technologies can significantly accelerate application outcomes.

• Collaborate with external semiconductor and accelerator companies to map specialized hardware capabilities to application-specific solution requirements.

  Required qualifications, capabilities, and skills

• Master’s degree with 3+ years of industry experiences, or Ph.D. degree with 1+ years of industry experience in computer science, physics, math, engineering or related fields.
• Strong background in computer architecture, accelerator systems (e.g., ASICs, wafer-scale engines, dataflow architectures, systolic arrays), or advanced compute platforms.
• Demonstrated understanding of modern accelerator chips and heterogeneous processing units, including experience with memory hierarchies, interconnects, and parallel processing.
• Ability to analyze and reason about performance, scalability, and feasibility of hardware solutions for AI and other data and compute intensive workloads.
• Demonstrated hands-on experience with AI (e.g., fast inference) or other data- and compute-intensive workloads on alternative chip architectures, with a strong emphasis on workload characterization and benchmarking.
• Strong analytical and quantitative skills, with the ability to clearly communicate complex architectural concepts to both technical and non-technical audiences.

Preferred qualifications, capabilities, and skills

• Background spanning both hardware architecture and algorithmic or application-level research.
• Hands-on experience with performance optimization and low-level tuning of application workloads on alternative chip architectures, for instance optimizing inference or training of AI workflows with custom kernel design.
• Experience spanning multiple accelerator architectures including custom ASICs, wafer-scale and dataflow systems.
• Experience working/collaborating with top AI hardware labs or accelerator platform teams.