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Senior Silicon Engineer

Microsoft

Microsoft

Posted on Dec 23, 2024

Senior Silicon Engineer

Bangalore, Karnataka, India

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Date posted
Dec 23, 2024
Job number
1796852
Work site
Up to 50% work from home
Travel
0-25 %
Role type
Individual Contributor
Profession
Hardware Engineering
Discipline
Silicon Engineering
Employment type
Full-Time

Overview

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission.

Are you seeking an opportunity to work on delivering silicon solutions that have a planet-scale impact? The Data Processing Unit (DPU) team within the Azure Hardware Systems & Infrastructure group is seeking a Senior Silicon Engineer. You will join our front-end silicon team and be responsible for delivering cutting-edge, high performance, low power, scalable and programmable DPU silicon.

Qualifications

  • BS and/or MS in Electrical Engineering or equivalent degree
  • 8+ years of RTL design and/or architecture experience
  • Knowledge of Compression, hardware offloading, programmable logic. Prior experience in designing Accelerator engines is a plus.
  • Experience on DDR and DDR controllers is a plus
  • Experience on ARM/RISC-V processor is a plus
  • Experience on PCI-e is a plus.
  • Proven track record with the definition and development of complex SoCs. In depth understanding of processors and peripheral interconnect bus protocols and architectures
  • High performance (low latency, high bandwidth) design techniques
  • Understanding of low power microarchitecture techniques. Strong knowledge of Verilog, System Verilog, Synthesis and Static Timing Analysis
  • Self-motivated and able to work effectively both independently and in a team.


#SCHIEINDIA

Responsibilities

As a Senior Silicon Engineer in the Data Processing Unit team, you will be responsible for RTL micro-architecture and design, solving complex problems in a datacenter. You will interact with the software team to co-develop a programmable silicon implementation. This position is expected to be highly visible and impactful. The vast breadth of domains required to build our DPU silicon gives the perfect opportunity to experience different areas of expertise. The depth required to solve complex engineering problems utilizes your experience and provides you with the perfect platform to shine and grow to the next stage in your career.


Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.
Industry leading healthcare
Educational resources
Discounts on products and services
Savings and investments
Maternity and paternity leave
Generous time away
Giving programs
Opportunities to network and connect

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.